Cache coherency is a vital issue in a shared-memory multiprocessor system. Cache coherency refers to providing an accurate and common view of memory to all devices that share the same memory system. To maintain coherency, snoopy protocols are used by processors to monitor, or snoop, a shared memory bus. The processors use the information snooped on the bus to ensure the memory is supplied with the latest modified data in cache.
In one example, a system controller maintains cache coherency between a processing unit and an Input/Output (I/O) device which masters transactions. The system controller is responsible for participating in the coherency protocol on behalf of the I/O device. The I/O device is unaware of a CPU cache, nor is it directly connected to the CPU bus.
A cacheline is the smallest granule of information about which coherency and validity within the cache is maintained. Typically a cacheline represents 32 bytes of data, but some systems could have finer granularity or courser depending upon the CPU architecture.
Different transfer types are used to maintain cache coherency. For example, a CLEAN transfer type is used for memory reads between 1–32 bytes. For a CLEAN transfer type, any modified data in the CPU cacheline is written to memory, and returned to the reading device. A FLUSH transfer type is used for memory writes between 1–31 bytes. The FLUSH causes any modified data in the CPU cache to be written to memory, the cacheline then becomes invalid. A KILL transfer type is used for writes of 32 bytes. The KILL transfer type causes the CPU cacheline to become invalid.
As described above, when a partial cacheline is being written into memory, the FLUSH transfer type is used. However, if the modified copy in cache is unimportant to the system, the KILL transfer type would be preferred, since the KILL transfer type invalidates the cacheline without the processor first having to store the contents of the cacheline into memory. The problem is that there is no way of telling when the modified copy in the cache is important.
Another problem occurs when a device reads from memory and the processor finds a hit for that cacheline. The processor will CLEAN its cache by updating memory while keeping the cacheline valid. This leaves the cacheline in an Exclusive state where the memory and the cacheline contain the same contents. However, in some situations it may be preferred to invalidate the cacheline so that it can be used to store other data.
The present invention addresses this and other problems associated with the prior art.